azog | April 26, 2009
So yea, I went to TCF this year. It’ll probably be the last year I go. From what I heard, it almost didn’t happen this year, and it that’s the case, I wouldn’t be surprised if it doesn’t happen next year. Which, if this year was an indication of the future, is going to be [...]
azog | April 23, 2009
When I stopped at Dunkin Donuts for coffee this morning, I noticed that my odometer hit exactly 6502. That just tickled me.
azog | April 17, 2009
And now for something completely different. From Overheard in the Office, an often funny, if sometimes crude feed. Quite nicely sums up my life. Engineer #1: How’s the baby? Engineer #2: Great! Engineer #1: I’m thinking of having one soon! Engineer #2: Really? You’re married? Engineer #1: No, working on it. Engineer #2: Oh, wow! [...]
azog | April 11, 2009
I need to step back from trying to learn how to program this CPLD. This is way over my head, at a very deep level that is beyond me. I’ve looked at dozens of tutorials on Verilog and VHDL, and actually decided that ABEL is the way to go. But you’re pretty much working at [...]
azog | April 6, 2009
Sorry to keep changing the theme so often. I’m still trying to find a tastefully simple theme, and having ZERO CSS skillz, I have to rely on someone elses intereptation of “tastefully simple”
azog | April 6, 2009
I love the AVR Dragon. Have I said that before? Well, I’ll say it again. At $50, you get a JTAG debugger, and it just doesn’t get any better than that. I think the JTAG-ICE cost like $300. And it’s not just for JTAG, it can do ISP and HVPP. It doesn’t support as many [...]
azog | April 5, 2009
For someone who really doesn’t have a clue, I’m kinda having fun playing with this CPLD kit. Right now, I’m using the schematic editor to do various simple things. But I’ve been reading about schematic versus HDLs (hardware description language), and I think I’ve come to an understanding that I really need to learn an [...]
azog | April 4, 2009
Having gone through the previous steps of creating a project, etc, but not really knowing where the pins are physically connected, I needed to open my eyes a little better. The report from implementation gave a whole slew of information on the target, but I did not notice the “Pins” link on that report… So [...]
azog | April 4, 2009
Continuing on with my CPLD learning (or non-learning) adventure, I did something, but I’m not exactly sure what. Create a new project, with my target hardware I added no sources during project creation, and can add them later Once the empty project was created, I added a source. Several different types are available: VHDL, Verilog, [...]
azog | April 3, 2009
Playing around with the CPLD starter kit some more, I realize that I am so over my head it is not funny. To begin with, the software itself is confusing. There are several tools. One is the “ISE WebPACK”, which appears to be only for CPLDs, and is supposedly free. Another higher-level tool is the [...]