Silent Q

Azog's little slice of the world. Whee.

Time to choose an HDL

Posted By on April 5, 2009

For someone who really doesn’t have a clue, I’m kinda having fun playing with this CPLD kit.

Right now, I’m using the schematic editor to do various simple things. But I’ve been reading about schematic versus HDLs (hardware description language), and I think I’ve come to an understanding that I really need to learn an HDL to some degree. The one example one tutorial gave was changing a few dozen 16-bit counters to 32-bit counters. For a schematic, you’d need to edit each page. For an HDL, you’d probably end up editing a single line of text.

So there are three that I can seemingly choose from: VHDL, Verilog, and ABEL. I’m spending my time looking at the three of them. ABEL appears to be more geared specifically towards CPLDs, while the other two can also be used in FPGAs. Do I care? This is not a career path for me, so I don’t know if I care about learning “obsolete” languages.

I quickly looked on Amazon to see if I could find some good books on Verilog, and quickly looked away. They’re all at least $100.

The “fitter report” of ISE WebPACK allows you to display the equations in all three. Here’s a simple test I made as a schematic. BTN1 goes to LD0, and also thru an inverter to LD1. The system clock goes to LD2. So I have two buffers and one inverter.


ck_out = ck_in;
inv_out = !inside;
outside = inside;


ck_out <= ck_in;
inv_out <= NOT inside;
outside <= inside;


_ck_out (ck_out, ck_in, 1'b0, 1'b0, 1'b0, 1'b1);
_inv_out (inv_out, !inside, 1'b0, 1'b0, 1'b0, 1'b1);
_outside (outside, inside, 1'b0, 1'b0, 1'b0, 1'b1);

Nice, huh?


One Response to “Time to choose an HDL”

  1. Vadim says:

    I’ve bean getting into FPGA programing lately. It’s interesting.
    I like VHDL But may give Verilog a try.

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